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L9825
Octal Low-side Driver For Resistive and Inductive Loads With Serial / Parallel Input Control, Output Protection and Diagnostic
s
OUTPUTS CURRENT CAPABILITY UP TO 1A, RON 0,75 AT TJ = 25C PARALLEL CONTROL INPUTS FOR OUTPUTS 1 AND 2 SPI CONTROL FOR OUTPUTS 1 TO 8 RESET FUNCTION WITH RESET SIGNAL AT NRES PIN OR UNDERVOLTAGE AT VCC INTRINSIC OUTPUT VOLTAGE CLAMPING AT TYP. 50V OVERCURRENT SHUTDOWN AT OUTPUTS 1 TO 6 SHORT CIRCUIT CURRENT LIMITATION AND SELECTIVE THERMAL SHUTDOWN AT OUTPUTS 7 AND 8 OUTPUT STATUS DATA AVAILABLE ON THE SPI
PowerSO20 ORDERING NUMBER: L9825
s s s
s s s
DESCRIPTION L9825 is a Octal Low-Side Driver Circuit, dedicated for automotive applications. Output voltage clamping is provided for flyback current recirculation, when inductive loads are driven. Chip Select and Serial Peripheral Interface for outputs control and diagnostic data transfer. Parallel Control inputs for two outputs.
s
BLOCK DIAGRAM
V CC
V CC
OUT1
1 2 3
NON1
Q1
S
Latch / Driver
R
I OL
Diag1
Fault Latch
+ -
VDG
CH1 NON2
V CC Q2 Diag2
CH2
OUT2 OUT3
SPI Interface
O utpu t Latch
NCS
V CC
CLK
V CC
Shift Register
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Diag1 Diag2 Diag3 Diag4 Diag5 Diag6 Diag7 Diag8
Q3
S
Latch / Driver
Diag3 Q4 Diag4 Q5 Diag5 Q6 Diag6
I OL R
+ -
VDG
CH3 CH4 CH5 CH6 OUT4 OUT5 OUT6 OUT7
SDI
SDO
V CC
V CC
Q7
S Latch / Driver Current Control R Overtemperature Detection
I OL
nRES
V CC
Reset
Undervoltage RESET
Reset
+
Diag7 Q8 Diag8
-
VDG
CH7 CH8 OUT8
GND
April 2003
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L9825
PIN CONNECTION (Top view)
GND NON1 SDO OUT1 OUT3 OUT5 OUT7 SDI CLK GND
1 2 3 4 5 6 7 8 9 10
POWSO20
20 19 18 17 16 15 14 13 12 11
GND NCS nRes OUT8 OUT6 OUT4 OUT2 Vcc NON2 GND
PIN DESCRIPTION
N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin GND NON1 SDO Out 1 Out 3 Out 5 Out 7 SDI CLK GND GND NON2 VCC Out 2 Out 4 Out 6 Out 8 nRes NCS GND device ground control input 1 serial data output output 1 output 3 output 5 output 7 serial data input serial clock device ground device ground control input 2 supply voltage output 2 output 4 output 6 output 8 asynchronous nRes chip select (active low) device ground Function
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L9825
ABSOLUTE MAXIMUM RATINGS For voltages and currents applied externally to the device:
Symbol VCC Supply voltage Parameter Value -0.3 to 7 Unit V
Inputs and data lines (NONx, NCS, CLK, SDI, nRes) VIN VIN IIN Voltage (NONx, NCS, CLK, SDI) Voltage (nRes) Protection diodes current 1) (T 1ms) -0.3 to 7 -0.3 to 7 -20 to 20 V V mA
Outputs (Out1 ... Out8) VOUTc IOUT EOUTcl Continuous output voltage Output current 2) Output clamp energy (IOUT 0.5A) -1.0 to 45 -3 to 2.05 20 V A mJ
Notes: 1. All inputs are protected against ESD according to MIL 883C; tested with HBM at 2KV. It corresponds to a dissipated energy E 0,2mJ. 2. Transient pulses in accordance to DIN40839 part 1, 3 and ISO 7637 Part 1, 3.
For currents determined within the device:
Outputs (Out1 ... Out8) IOUT IOUT Output current (Out1 ... Out6) Output current (Out7, Out8) Total average-current all outputs 3) 2.05 1.75 4.5 (Min.) A A A
3. When operating the device with short circuit at more than 2 outputs at the same time, damage due to electrical overstress may occur.
THERMAL DATA
Symbol Thermal shutdown TJSC Thermal shutdown threshold Min. Typ. 150 165 C C Parameter Value Unit
Thermal resistance Rthjc-one Rthjc-all Single output (junction case) Max. All outputs (junction case) Max. 13 1.6 C/W C/W
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L9825
ELECTRICAL CHARACTERISTCS (4.5V VCC 5.5V; -40C TJ 150C; unless otherwise specified)
Symbol Supply voltage IccSTB IccOPM Standby current Operating mode without load IOUT1 ... 8 = 500mA SPI - CLK = 3MHz NCS = LOW SDO no load Iout = -3A 5 5 mA mA Parameter Test Condition Min. Typ. Max. Unit
ICC
ICC during reverse output current
100
mA
Inputs (NONx. NCS, CLK, SDI, nRes) VINL VINH Vhyst IIN RIN CIN Low level High level Hysteresis voltage Input current Pullup resistance Input capacitance VIN = VCC 50 -0.3 0.7*VCC 0.85 10 250 10 0.2*VCC VCC+0.3 V V V A k pF
Serial data outputs VSDOH VSDOL ISDOL CSDO High output level Low output level Tristate leakage current Output capacitance ISDO = -4mA ISDO = 3,2mA NCS = high; 0V VSDO VCC fSDO = 300kHz -10 VCC -0.4 0.4 10 10 V V A pF
Outputs OUT 1 ... 8 IOUTL1 - 8 Leakage current IOUTL1 - 8 Leakage current IOUTL1 - 8 Leakage current Vclp RDSon COUT Output clamp voltage On resistance OUT 1 ... 8 Output capacitance OUTx = OFF; VOUTx = 25V; VCC = 5V OUTx = OFF; VOUTx = 16V; VCC = 5V OUTx = OFF; VOUTx = 16V; VCC = 1V 1mA Iclp Ioutp; Itest = 10mA with correlation IOUT = 500mA; Tj = +150C VOUT = 16V; f = 1MHz 45 100 100 10 60 1.5 300 A A A V W pF
Outputs short circuit protection ISBC ILIM tSCB Overcurrent shutoff threshold Short circuit current limitation Delay shutdown OUT1 ... OUT6 OUT7; OUT8 for output 1 ... 6; IOUT 1/2 ISBC 1.05 1.05 0.2 1.4 1.4 3 2.05 1.75 12 A A s
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L9825
ELECTRICAL CHARACTERISTCS (continued) (4.5V VCC 5.5V; -40C TJ 150C; unless otherwise specified)
Symbol Diagnostics VDG IOL tdf Diagnostic threshold voltage Open load detection sink current Diagnostic detection filter time for output 1 & 2 on each diagnostic condition Vout = VDG 0.32*VCC 20 15 0.4*VCC 100 50 V A s Parameter Test Condition Min. Typ. Max. Unit
Outputs timing tdon1 tdon2 tdoff Turn ON delay of OUT 1 and 2 Turn ON delay of OUT 3 to 8 Turn OFF delay of OUT 1 to 8 NON1, 2 = 50% to VOUT = 0.9*Vbat NCS = 50% to VOUT = 0.9*Vbat NCS = 50% to VOUT = 0.9*Vbat NCS = 50% to VOUT = 0.1*Vbat NON1, 2 = 50% to VOUT = 0.1*Vbat For output 3 to 8; 90% to 30% of Vbat; RL = 500; Vbat = 16V For output 1 and 2; 90% to 30% of Vbat; RL = 500; Vbat = 16V For output 1 to 8; 30% to 90% of Vbat; RL = 500; Vbat = 16V For output 1 to 8; 30% to 80% of Vbat; RL = 500; Vbat = 0.9 * Vclp 0.7 2 2 2 5 10 10 3.5 10 10 15 s s s V/s V/s V/s V/s
dUon1/dt Turn ON voltage slew-rate dUon2/dt Turn ON voltage slew-rate dUoff1/dt Turn OFF voltage slew-rate dUoff2/dt Turn OFF voltage slew-rate
Serial diagnostic link (Load capacitor at SDO = 100pF) fclk tclh tcll tpcld tcsdv tsclch thclcl tscld thcld tsclcl thclch tpchdz Clock frequency Minimum time CLK = HIGH Minimum time CLK = LOW Propagation delay CLK to data at SDO valid NCS = LOW to data at SDO active CLK low before NCS low CLK change L/H after NCS = low SDI input setup time SDI input hold time CLK low before NCS high CLK high after NCS high NCS L/H to output data float NCS pulse filter time Multiple of 8 CLK cycles CLK change H/L after SDI data valid SDI data hold after CLK change H/L 150 150 100 Setup time CLK to NCS change H/L 100 100 20 20 4.9V VCC 5.1V 50% duty cycle 3 160 160 100 100 MHz ns ns ns ns ns ns ns ns ns ns ns
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L9825
FUNCTIONAL DESCRIPTION General The L9825 integrated circuit features 8 power low-side-driver outputs. Data is transmitted to the device using the Serial Peripheral Interface, SPI protocol. Outputs 1 and 2 can be controlled parallel or serial. The power outputs features voltage clamping function for flyback current recirculation and are protected against short circuit to Vbat. The diagnostics recognizes two outputs fault conditions: 1) overcurrent for outputs 1 to 6 , overcurrent and thermal overload for outputs 7 and 8 in switch-on condition and 2) open load or short to GND in switch-off condition for all outputs. The outputs status can be read out via the serial interface. The chip internal reset is a OR function of the external nRes signal and internally generated undervoltage nRes signal. Output Stages Control Each output is controlled with its latch and with common reset line, which enables all eight outputs. Outputs 1 and 2 can be controlled also by its NON1, NON2 inputs. It allows PWM control independently on the SPI. These inputs features internal pull-up resistors to assure that the outputs are switched off, when the inputs are open. The control data are transmitted via the SDI input, the timing of the serial interface is shown in Fig. 1. The device is selected with low NCS signal and the input data are transferred into the 8 bit shift register at every falling CLK edge. The rising edge of the NCS latches the new data from the shift register to the drivers. Figure 1. Timing of the Serial Interface
NCS
tsclch thclcl tclh tcll tsclcl thclch
CLK
tcsdv tpcld not defined tscld D8 thcld tpchdz D1
SDO
SDI
D8
D7
D1
The SPI register data are transferred to the output latch at rising NCS edge. The digital filter between NCS and the output latch ensures that the data are transferred only after 8 CLK cycles or multiple of 8 CLK cycles since the last NCS falling edge. The NCS changes only at low CLK. Table 1. Outputs Control
Outputs 1, 2: NON1,2 SPI-bit 1,2 Output 1, 2 1 0 off 0 0 on 0 1 on 1 1 on SPI-bit 3...8 Output 3...8 0 off 1 on Outputs 3 to 8:
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L9825
Figure 2. Output Control register structure
MSB Q2 Q4 Q6 Q8 Q1 Q3 Q5 LSB Q7
Control-bit output 7 Control-bit output 5 Control-bit output 3 Control-bit output 1 Control-bit output 8 Control-bit output 6 Control-bit output 4 Control-bit output 2
Power outputs characteristics for flyback current, outputs short circuit protection and diagnostics For output currents flowing into the circuit the output voltages are limited. The typical value of this voltage is 50V. This function allows that the flyback current of a inductive load recirculates into the circuit; the flyback energy is absorbed in the chip. Output short circuit protection for outputs 1 to 6 (dedicated for loads without inrush current): when the output current exceeds the short circuit threshold, the corresponding output overload latch is set and the output is switched off immediately. Output short circuit protection for outputs 7 and 8 (dedicated for loads with inrush current, as lamps): when the load current would exceed the short circuit limit value, the corresponding output goes in a current regulation mode. The output current is determined by the output characteristics and the output voltage depends on the load resistance. In this mode high power is dissipated in the output transistor and its temperature increases rapidly. When the power transistor temperature exceeds the thermal shutdown threshold, the overload latch is set and the corresponding output switched off. For the load diagnostic in output off condition each output features a diagnostic current sink, typ 60A. Diagnostics The output voltage at all outputs is compared with the diagnostic threshold, typ 0.38 * VCC. Outputs 1 and 2 features dedicated fault latches. The output status signal is filtered and latched. The fault latches are cleared during NCS low. The latch stores the status bit, so the first reading after the error occurred might be wrong. The second reading is right. Table 2. Diagnostic for outputs 1 and 2 in parallel controlled mode.
Output 1, 2 off off on on Output-voltage > DG-threshold < DG-threshold < DG-threshold > DG-threshold Status-bit high low high low Output-mode correct operation fault condition 2) correct operation fault condition 1)
Fault condition 1) "output short circuit to Vbat" : the output was switched on and the voltage at the output exceeded the diagnostics threshold due to overcurrent, the output overload latch was set and the output has been switched off. The diagnostic bit is low.
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L9825
Fault condition 2) "open load" or "output short circuit to GND" : the output is switched off and the voltage at the output drops below the diagnostics threshold, because the load current is lower than the output diagnostic current source, the load is interrupted. The diagnostic bit is low. For outputs 3 to 8 the output status signals, are fed directly to the SPI register. Table 3. Diagnostic for outputs 1 to 8 in SPI controlled mode.
Output 1 ... 8 off off on on Output-voltage > DG-threshold < DG-threshold < DG-threshold > DG-threshold Status-bit high low low high Output-mode correct operation fault condition 2) correct operation fault condition 1)
The fault condition 1) "output short circuit to Vbat" : For outputs 3 to 6 is the same as of outputs 1 and 2. For outputs 7 and 8 : the output was switched on and the voltage at the output exceeds the diagnostics threshold. The output operates in current regulation mode or has been switched off due to thermal shutdown. The status bit is low. Fault condition 2) "open load" or "output short circuit to GND" is the same as of outputs 1 and 2. At the falling edge of NCS the output status data are transferred to the shift register. When NSC is low, data bits contained in the shift register are transferred to SDO output et every rising CLK edge. Figure 3. The Pulse Diagram to Read the Outputs Status Register
NCS CLK SDI SDO MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB
MSB
Figure 4. The Structure of the Outputs Status Register
MSB LSB
Diag2 Diag4 Diag6 Diag8 Diag1 Diag3 Diag5 Diag7
Diagnostic-bit output 7 Diagnostic-bit output 5 Diagnostic-bit output 3 Diagnostic-bit output 1 Diagnostic-bit output 8 Diagnostic-bit output 6 Diagnostic-bit output 4 Diagnostic-bit output 2
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L9825
APPLICATION NOTES Figure 5. Typical Application Circuit Diagram
L9825
L9825
For higher current driving capability two outputs of the same kind can be paralleled. In this case the maximum flyback energy should not exceed the limit value for single output. The immunity of the circuit with respect to the transients at the output is verified during the characterization for Test Pulses 1, 2 and 3a, 3b, DIN40839 or ISO7637 part 3. The Test Pulses are coupled to the outputs with 200pF series capacitor. All outputs withstand testpulses without damage. The correct function of the circuit with the Test Pulses coupled to the outputs is verified during the characterization for the typical application with R = 16W to 200W, L= 0 to 600mH loads. The Test Pulses are coupled to the outputs with 200pF series capacitor.
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L9825
mm MIN. 0.1 0 0.4 0.23 15.8 9.4 13.9 1.27 11.43 10.9 5.8 0 15.5 0.8 11.1 2.9 6.2 0.1 15.9 1.1 1.1 0.031 8 (typ.) 8 (max.) 10 0.394 0.228 0.000 0.610 0.429 TYP. MAX. 3.6 0.3 3.3 0.1 0.53 0.32 16 9.8 14.5 0.000 0.016 0.009 0.622 0.370 0.547 0.050 0.450 0.437 0.114 0.244 0.004 0.626 0.043 0.043 JEDEC MO-166 0.004 MIN. inch TYP. MAX. 0.142 0.012 0.130 0.004 0.021 0.013 0.630 0.386 0.570
Weight: 1.9gr
DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 G H h L N S T
OUTLINE AND MECHANICAL DATA
(1) "D and E1" do not include mold flash or protusions. - Mold flash or protusions shall not exceed 0.15mm (0.006") - Critical dimensions: "E", "G" and "a3".
PowerSO20
N
N a2 b e A
R
c DETAIL B a1 E DETAIL A
DETAIL A e3 H
lead
D a3 DETAIL B
20 11
Gage Plane 0.35
slug
-C-
S E2 T E1 BOTTOM VIEW
L
SEATING PLANE G C
(COPLANARITY)
E3
1 10
h x 45
PSO20MEC
D1
0056635
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L9825
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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